1. Technical Field
The present invention relates to a system and method for an improved DMA controller translation mechanism. More particularly, the present invention relates to a system and method for storing real page numbers in DMA command fields in order to use the real page numbers during a DMA command rollout.
2. Description of the Related Art
Computer system applications typically specify an effective address or indirect address to store and retrieve data. In order to carry out a data storage or retrieval request, the computer system translates the effective address to a real or physical address, which corresponds to a physical location in memory.
The computer system typically includes a memory management unit (MMU) to provide effective address to real address translation. In one configuration, a DMA queue always accesses the MMU for all load and store instructions for address translation, which increases latency and consumes more power.
Another configuration uses an effective to real address translator (ERAT) in combination with a secondary level MMU. An ERAT includes a lookup table that stores prior address translations. When the DMA queue sends a DMA request (including an effective address) to the ERAT, the ERAT looks in its lookup table for an effective address match. If there is a match, the ERAT provides the corresponding real address, and the MMU access is bypassed. However, if the ERAT does not locate an entry corresponding to the DMA request's effective address, the ERAT sends a “miss” to the MMU which, in turn, performs the same steps as discussed in the first configuration above.
When the MMU identifies a corresponding real page number, the MMU sends the real page number to the ERAT, which the ERAT loads in its table. Using this configuration, the ERAT provides a circuit performance improvement since the MMU does not need to be accessed when the ERAT matches the effective address. However, a challenge found is that in order for the ERAT to get good “hit rates,” the ERAT's lookup table must include a large number of entries, which may consume a large amount of power and physical area. In addition, another challenge found is that the ERAT still performs a lookup for each DMA request, which also increases the latency.
What is needed, therefore, is a system and method for an improved effective address to real address translation mechanism.